1. Field of the Invention
This invention relates to the testing of electrical delay circuits which have controllable delay characteristics. The invention also relates to clock generator circuits employed within, for example, microprocessing units.
2. Description of the Relevant Art
An electrical delay element is typically associated with an output signal which is an image of the input signal delayed by a certain amount of time. Most delay elements have either a fixed delay time or a delay time that varies in a specified way in accordance with a control signal. Testing such delay elements for manufacturing defects can often be simply a matter of comparing their delay with a known reference delay.
A plurality of identical variable delay elements that form a delay chain may be employed within a clock signal generator to synthesize, for example, an internal microprocessor clock signal. Although it is relatively simple to fabricate virtually identical delay elements on a single integrated circuit chip, batch-to-batch variations due to processing variations make it very difficult to fabricate a delay element in which a certain control input value will always yield the same fixed time delay. Fortunately, with respect to the above-mentioned clock signal generators, it is only necessary that the relative delays of the variable delay elements within a particular clock generator be essentially identical. The actual delay values are not critical. In view of this, it may not be possible or may not be cost-effective to test this class of delay element by simple comparison with a known reference delay.
A further consideration with respect to the test of delay elements is the type of possible defects. In an integrated circuit manufacturing test, it is assumed that the fundamental design of the delay element is sound and that only failures introduced by manufacturing defects remain. A manufacturing defect will not necessarily cause the delay element to fail entirely but may rather subtly or dramatically affect the relationship between the control input and the time delay of the delay element. Complete failure of the delay element is easily detected, but subtle manufacturing defects in delay elements are very difficult to detect.
Accordingly, a test configuration and method are desirable wherein variably controlled delay elements embodied within, for example, a clock generator circuit may be readily tested for subtle defects without the need for costly calibration of individual delay elements.